Quantum Compilation & Transpilation

The compiler translates your gates into the device's native set, assigns each logical qubit a physical location, and inserts routing operations so every two-qubit gate lands on connected qubits. The executed circuit implements the same computation but can differ in gate count, depth, and which physical wire carries each result.

A native gate is one the hardware can execute directly as a calibrated control pulse; everything else must be rewritten into natives. A small universal basis can build any gate exactly or to a stated tolerance, so a short native list does not proportionally weaken a processor.

Mapping is the one-to-one assignment of your program's logical qubits to physical qubits on the chip. A good initial layout puts frequently interacting qubits on adjacent, well-calibrated hardware, and the mapping record tells you which physical readout belongs to which logical qubit.

The coupling map is the graph of qubit pairs that can interact directly; a two-qubit gate between unconnected qubits cannot run as written. Routing moves states until the operands are adjacent, and every unit of distance costs extra entangling gates, so distance translates directly into error.

A SWAP exchanges the full states of two qubits, so after every SWAP the compiler must update its logical-to-physical mapping table or later gates hit the wrong qubits. On most gate-based hardware one SWAP costs three CX gates, so SWAP count, native two-qubit count, and depth must be read together.

Decomposition rewrites an unsupported gate as a sequence of native ones, either exactly (up to an unmeasurable global phase) or approximately within a declared tolerance. Equivalent decompositions can trade gate count against depth and calibration quality, so shorter is not automatically better.

Depth is the number of time-steps a circuit needs when gates that touch different qubits run in parallel. Compilers reduce it by cancelling gate pairs that undo each other and by packing independent gates into the same layer — but only rewrites that provably leave the output unchanged are allowed.

Hardware-aware compilation uses measured, time-stamped error data to choose among the many valid ways of placing and routing a circuit — and sometimes a longer route through better qubits beats the shortest one. Every choice must record which calibration snapshot and which random seed it used, or the result cannot be reproduced or audited.

On a superconducting chip each qubit talks only to fixed neighbours, so distant interactions pay a SWAP tax of extra two-qubit gates; trapped-ion machines let any pair interact directly but run two-qubit gates far more slowly. Neither architecture wins universally — the outcome depends on the circuit's interaction pattern and on which cost your objective weighs.

Total gate count is a single number that hides gate type, parallelism, duration, and error rates, so the candidate with the fewest gates can lose on estimated fidelity or runtime. Choosing between compiled circuits requires an explicit objective function — and different reasonable objectives rank the same candidates differently.

A compilation report is a reproducibility record: input hash, compiler and target versions, seed, qubit mapping, and before/after metrics. It is trustworthy when you can trace every added gate to a specific translation or routing step and reconcile the arithmetic — and unauditable when the mapping or provenance is missing.

The capstone compiles one fixed logical circuit for line, grid, and all-to-all targets, then explains every difference in gate count, depth, and estimated fidelity with explicit arithmetic. The deliverable is a sourced, reproducible comparison report — not a verdict on which QPU is best.