Basis and Native Gates
A native gate is one the hardware can execute directly as a calibrated control pulse; everything else must be rewritten into natives. A small universal basis can build any gate exactly or to a stated tolerance, so a short native list does not proportionally weaken a processor.
Why can't the chip just run an H gate?
On real hardware a gate is not a lookup — it is a physical control action: a shaped microwave or laser pulse, calibrated for one specific operation on one specific qubit. The short list of operations a device implements this way is its native gate set.
Everything else must be rewritten. The compiler picks a basis — the set of gates it will target, normally the natives — and performs basis translation: replacing each gate in your circuit with a sequence from that basis that does the same job.
This resembles lowering a programming language to a CPU's instruction set. The analogy breaks in two places: quantum translation must track a subtlety called global phase (defined below), and some translations are deliberately approximate — correct only within a stated error tolerance, which must be reported alongside the result.
Worked example: building H from native-style gates
Suppose H (the Hadamard gate, which turns state 0 into an equal mix of 0 and 1) is not native, but Z (a sign flip on state 1's amplitude) and RY rotations (turns by a chosen angle about the Y axis) are. The identity H = RY(π/2) · Z holds exactly: apply Z first, then rotate by a quarter turn.
Check it on input 0, carrying the numbers. Z leaves state 0 alone — the amplitudes stay (1, 0). RY(π/2) sends amplitude 1 on state 0 to cos(π/4) ≈ 0.707 on state 0 plus sin(π/4) ≈ 0.707 on state 1. Result: amplitudes (0.707, 0.707) — exactly what H gives; squaring each gives 50% / 50%.
Check input 1. Z flips the sign of state 1: amplitudes go from (0, 1) to (0, −1). RY(π/2) mixes them by a fixed rule of its own, like H's add-and-subtract machine but with the minus on the other row: new 0-amplitude = 0.707 × (old 0-amplitude) − 0.707 × (old 1-amplitude), and new 1-amplitude = 0.707 × (old 0-amplitude) + 0.707 × (old 1-amplitude). Apply it: new state-0 amplitude = 0.707 × 0 − 0.707 × (−1) = +0.707; new state-1 amplitude = 0.707 × 0 + 0.707 × (−1) = −0.707. That is (0.707, −0.707) — precisely H applied to input 1, sign included.
Because gates act linearly, matching amplitudes on both basis inputs means the translation is exact for every input. Note that matching measurement percentages alone would not be enough — the minus sign matters as soon as another gate follows.
The textbook Bell pair
The same Bell pair in a CZ-based gate set
Worked example: making CX out of CZ
Many superconducting devices natively implement CZ — a gate that flips the sign of the amplitude only when both qubits are 1 — rather than CX, which flips the value of the target bit when the control is 1. The standard translation is: H on the target, CZ, H on the target again.
Walk the input "control = 1, target = 0". The first H puts the target at amplitudes (0.707, 0.707), so the joint state is 0.707 on (control 1, target 0) plus 0.707 on (control 1, target 1). CZ flips the sign of the both-1 part, leaving the target at (0.707, −0.707). The second H maps (0.707, −0.707) exactly to state 1. Net effect: the target flipped from 0 to 1 — which is what CX must do when the control is 1. (In the runnable circuit above we drew the two target-side gates as H for readability; a strict native pass would expand them exactly as in the previous worked example.)
One loose end: translations only need to match up to global phase — a single overall factor multiplying the whole state. Measurement probabilities are squared magnitudes, so that factor cancels out of every possible experiment. For instance the S gate and the rotation RZ(π/2) differ only by such a factor, and no experiment can tell them apart.
Finally, the size of the native list is a poor proxy for capability. A handful of gates can be universal — able to build any operation to any desired accuracy — so a processor with four native gates is not "half as capable" as one with eight. What matters is the cost and quality of the sequences the compiler produces.
Which gate sets do real devices use?
Native sets differ by platform: superconducting chips typically calibrate one entangling gate (CZ or a CX-like variant) plus a few single-qubit rotations; trapped-ion systems calibrate a different entangling family. Compare declared gate sets side by side on the hardware comparison page, and treat any unlisted value as not publicly disclosed rather than guessing.