Hardware-Aware Compilation
Hardware-aware compilation uses measured, time-stamped error data to choose among the many valid ways of placing and routing a circuit — and sometimes a longer route through better qubits beats the shortest one. Every choice must record which calibration snapshot and which random seed it used, or the result cannot be reproduced or audited.
What extra information does the compiler get?
Earlier lessons treated the target machine as a wiring diagram: a topology (which pairs of physical qubits can run a two-qubit gate) and a native gate set. That is enough to produce a valid circuit. But real machines are uneven: on the same chip, one qubit link might fail 0.5% of the time while its neighbour fails 3% of the time.
Calibration data is the set of measured error rates and timings — per qubit, per link, per operation — that the vendor publishes after testing the machine, each value stamped with the time it was measured. Hardware-aware compilation means using this data to choose among the many valid compiled circuits: which physical qubits to use (layout, also called mapping), which paths to route interactions along, and which of several equivalent rewrites to keep.
The choice is scored by an objective function: an explicit formula combining costs such as gate count, depth, duration, and estimated error. "Best" only means "best under this objective, given this calibration snapshot".
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