Hardware-Aware Compilation

Hardware-aware compilation uses measured, time-stamped error data to pick among the many valid ways to place and route a circuit. Sometimes a longer route through better qubits beats the shortest one. Every choice must record which error snapshot and which random seed it used. Without that, nobody can repeat or check the result.

What extra information does the compiler get?

Why care? Two qubits on the same chip can differ in quality by a lot. Picking the good ones can cut your errors by more than any clever gate trick.

Earlier lessons treated the chip like a wiring diagram. It had a topology, which says which pairs of physical qubits can run a two-qubit gate. And it had a native gate set, the gates the chip can do directly. That is enough to make a valid circuit. But real chips are uneven. On the same chip, one qubit link might fail 0.5% of the time while its neighbour fails 3% of the time.

Calibration data is the set of measured error rates and timings. There are values for each qubit, each link and each operation. The vendor publishes them after testing the machine, and each value is stamped with the time it was measured.

Hardware-aware compilation means using this data to choose among the many valid compiled circuits. It decides three things:

which physical qubits to use (the layout, also called the mapping),
which paths to route qubit states along,
which of several equal rewrites to keep.

An everyday example: planning a drive with a live traffic app. The shortest road is not always the fastest. The app checks today's traffic before it picks. Here the example breaks. A traffic app sees traffic right now. A compiler sees error rates from the last test, which may already be a little old.

The choice is scored by an objective function. That is a clear formula that adds up costs like gate count, depth, time and expected error. "Best" only means "best under this formula, using this snapshot of calibration data".