Cross-QPU Compilation Capstone

In the capstone, you compile one fixed logical circuit for three kinds of chip: a line, a grid, and all-to-all. Then you explain every difference in gate count, depth and expected success with arithmetic anyone can check. What you hand in is a sourced, repeatable comparison report. It is not a verdict on which QPU is best.

What is the project?

Why care? Real choices about chips need more than a gut feeling. This project trains you to compare fairly and show your work.

Everything in this course comes together here. The task: take one logical circuit of 3 to 5 qubits and keep it fixed. Compile it for at least three types of target chip. Then write a comparison report. In it, trace every real difference to a specific cause. That means every extra gate, every extra layer of depth (the number of time steps), and every point of expected success. Back each one with arithmetic anyone can recheck.

The three archetype targets are simple model chips, not real devices:

Line: qubits in a row, each wired only to the ones right next to it. This is the harshest common wiring.
Grid: qubits in a rectangle pattern, each with up to four neighbours. This is the superconducting-chip archetype.
All-to-all: any pair can work together directly. This is the trapped-ion archetype.

Keeping the logical circuit fixed is your control, like in a science fair test. An everyday example: to test which of three ovens bakes best, you bake the same cake recipe in each. Here the example stops short. Ovens differ in one main way, heat. Chips differ in several ways at once: wiring, gate speed and error rates. But because only the target changes, every difference in the output comes from the target, not from the problem.