Qubit Mapping
Mapping is the one-to-one assignment of your program's logical qubits to physical qubits on the chip. A good initial layout puts frequently interacting qubits on adjacent, well-calibrated hardware, and the mapping record tells you which physical readout belongs to which logical qubit.
What is a qubit mapping?
Your program numbers its qubits 0, 1, 2 — these are logical qubits, names for roles in an algorithm. The chip has physical qubits: actual circuit elements at fixed positions, each with its own individually measured error rates.
A mapping (the starting choice is called the initial layout) is a one-to-one assignment of each logical qubit to a physical one. Logical q0 has no special claim on physical qubit 0; the compiler places it wherever the whole circuit runs cheapest.
The choice matters twice. It fixes how far apart interacting qubits start — and therefore how much routing is needed later — and it decides which of the chip's better or worse calibrated gates your circuit is exposed to.
Worked example: two layouts, one circuit, different bills
Circuit: a CX between logical q0 and q1, then a CX between logical q1 and q2. Chip: three physical qubits in a line, p0–p1–p2, connected only between neighbours.
Layout A: q0→p0, q1→p1, q2→p2. Both CXs land on connected pairs. Cost: 2 two-qubit gates.
Layout B: q1→p0, q0→p1, q2→p2. The first CX (q0–q1) runs on p1–p0: connected, fine. The second (q1–q2) needs p0–p2: not connected. The compiler must insert one SWAP — an exchange of two neighbouring qubits' states, costing 3 CX gates on most hardware — to bring them together. Cost: 2 + 3 = 5 two-qubit gates.
At 99% success per two-qubit gate, layout A finishes cleanly with probability 0.99 × 0.99 ≈ 0.980, so about 20 corrupted shots per 1000. Layout B gives 0.99⁵ ≈ 0.951 — about 49 per 1000. Same program, roughly 2.5 times the corruption, purely from placement.
A Bell pair on adjacent wires
The compiler relocates half the pair
Worked example: placing next to the good gates
Mapping is not only about distance. Suppose today's calibration reports a two-qubit error of 0.5% on the p0–p1 connection and 2% on p1–p2 — a spread you will genuinely see in daily device data.
For a single-CX circuit, placing the pair on p0–p1 gives success 0.995: about 5 corrupted shots per 1000. Placing it on p1–p2 gives 0.98: about 20 per 1000. Four times the error rate, decided entirely by layout. This is why serious compilers read the day's calibration before choosing, and why two-qubit fidelity is reported per connection rather than as one number for the whole chip.
One record must survive all of this: the final mapping table. Measurement hands you physical bits; without the table you cannot say which logical qubit each bit belongs to. The common assumption that logical q0 must run on physical qubit 0 fails on the very first optimized layout you meet.
Layout against a live device
On real devices the error map changes with every calibration cycle, so yesterday's best layout can be today's mediocre one. Browse per-device data on the QPU index; claims about a specific machine should come from dated observations, not from the archetypes used in these lessons.