The Circuit You Write Is Not the Circuit the QPU Runs

The circuit you draw in a notebook or in the Lab is a logical circuit: a statement of intent. It says "apply these operations to these numbered qubits, in this order" and quietly assumes any qubit can interact with any other.

Real processors do not offer that. Each device has an instruction set — the short list of operations its control electronics can actually perform — and a topology: a fixed map of which qubit pairs are physically wired together.

A compiler (often called a transpiler in quantum toolkits) rewrites your logical circuit into a physical circuit: one that uses only supported operations, applied only to connected pairs. That physical circuit is what the machine executes.

The analogy to a classical compiler turning C into machine code is fair, with one honest caveat: a classical compiler's choices mostly change speed, while a quantum compiler's choices change how often the answer is wrong, because every added operation carries a small error probability.

Compilation is a pipeline of transformations:

• Translate each gate into the device's native gate set.
• Map each logical qubit to a physical qubit.
• Route: insert movement operations so two-qubit gates land on connected pairs.
• Optimize: cancel and merge gates where the mathematics allows.
• Schedule: fix the timing of every control pulse (on some platforms).

Worked example. Take a two-operation logical circuit: an H (Hadamard, which puts a qubit into an equal superposition) on qubit 0, then a CX (controlled-NOT: flip the target qubit whenever the control qubit is 1) from qubit 0 to qubit 2. Target it at a three-qubit chip wired in a line, where qubit 0 connects only to 1, and 1 only to 2.

The CX between qubits 0 and 2 cannot run: they are not connected. The compiler inserts a SWAP — an operation that exchanges the states of two neighbouring qubits — to move qubit 0's state next to qubit 2. On most hardware a SWAP is itself built from 3 CX gates.

Count the cost. You wrote 2 operations containing 1 two-qubit gate. The chip runs H + SWAP + CX: with the SWAP expanded that is 1 + 3 + 1 = 5 operations, 4 of them two-qubit gates. If each two-qubit gate succeeds 99% of the time, the chance of an error-free run drops from 0.99 to 0.99 × 0.99 × 0.99 × 0.99 ≈ 0.961 — roughly 4 corrupted shots in every 100 instead of 1.

Both runs implement the same idea: put one qubit into an equal superposition, then correlate a second qubit with it. The H gate turns amplitude 1 on state 0 into amplitude 1/√2 ≈ 0.707 on each of 0 and 1. An amplitude is the number attached to each possible outcome; squaring it gives that outcome's probability. Here (1/√2) squared is exactly 1/2, so about 500 of 1000 shots land on each bar.

The difference between the runs is bookkeeping. In the routed version the SWAP moved qubit 0's state onto physical wire 1, so the correlated pair reads out on q1 and q2. The compiler records this final mapping — which physical wire holds which logical qubit — and interpreting your results depends on that record.

Two things follow. First, many different physical circuits validly implement the same logical circuit; compilers differ, and one logical circuit has no single "correct" compiled form. Second, the common belief that the hardware runs your diagram exactly as drawn is false on essentially every current device: something translates, maps, and routes it first. QPU137's compiled outputs are reference-compiler results for teaching, not predictions of any vendor compiler's exact output.

The simulator above is noiseless, so the routed and direct versions score identically. On hardware every inserted gate costs fidelity, and two-qubit gates dominate: compare devices on the two-qubit fidelity metric page.

Vendor compilers also target different native gate sets and topologies — browse them on the QPU index. When a device's specification is not published, the honest value is "not publicly disclosed", not an estimate.