Pricing…Open Lab
Hardware reality · after two-qubit gates · ~9 min

Circuit depth and width

Width is how many qubits a circuit uses. Depth is how many steps in a row it takes, once every gate that can run at the same time has been grouped together. On today's hardware, the numbers that best predict a good result are the two-qubit gate count and the two-qubit depth, because two-qubit gates make roughly ten times more errors than one-qubit gates.

What do depth and width actually measure?

Width is the easy one. It is the number of qubits the circuit touches.

Depth is more interesting. Each gate must wait for every earlier gate that uses any of the same qubits. Gates on different qubits can run at the same time. Depth is the number of time steps you are left with after you run as much as possible at once. Computer scientists call this path of waiting the critical path.

Think of making breakfast. You can boil the kettle and toast bread at the same time. But you can't pour the tea until the water boils. Gate count is the total amount of work. Depth is how long you wait on the clock.

QPU137 finds the depth with ASAP layering, short for "as soon as possible." It goes through the gates in order. It puts each one in the earliest layer where all of its qubits are free. A few more rules:

  • Every gate takes up one layer on every qubit it touches.
  • A barrier (a marker that says "don't move gates past here") starts a new layer but adds no depth.
  • A measurement counts as one layer.

The Lab shows depth, two-qubit gates, and two-qubit depth live as you edit. The full definition is on the circuit-depth metric page.

Why do two-qubit gates dominate the error budget?

On today's devices, each kind of step goes wrong at a very different rate:

  • single-qubit gates: about 0.01–0.1% of the time
  • two-qubit gates, which entangle (link) qubits: about 0.1–2%
  • readout: about 0.5–3% for each qubit you measure

The exact numbers change from platform to platform. They also drift each time a machine is re-tuned. But the order never changes. The two-qubit gates are the expensive ones. They are roughly ten times worse than single-qubit gates on every current type of machine.

Errors multiply. Say each two-qubit gate works 99% of the time. That rate of success is called its fidelity. Run 50 of them and the chance that none failed is 0.99 × 0.99 × … fifty times. Let's compute it: 0.99^50 ≈ 0.60. So about 40% of your signal is gone before you even count readout errors. It is like a chain of 50 people passing a message. Even if each person gets it right 99 times out of 100, the whole chain often gets it wrong.

That is why good tools report the two-qubit count apart from the total. It is also why two-qubit depth matters so much. That is the number of layers that hold at least one two-qubit gate. It is the single best guide to whether a circuit's output is signal or noise.

Here is what kind of claim this is. In the math, gates are perfect and depth costs nothing. Those are proven facts about the model. The error rates above are measured facts about today's machines. They get better every year. None of them is a law of nature.

What does a chain of waiting gates look like?

Four gates, but each CX waits for the one before it. So depth equals gate count here. Expect only 0000 and 1111, near 50/50.standby
12345q0|0⟩q1|0⟩q2|0⟩q3|0⟩H
press run to acquire
counts: sampledamplitudes: statevector, exactengine: in-browser

How does ASAP layering assign depth?

Let's walk through the circuit above, layer by layer.

  1. H on q0 goes in layer 1.
  2. CX 0,1 needs q0, so it goes in layer 2.
  3. CX 1,2 needs q1, so it goes in layer 3.
  4. CX 2,3 needs q2, so it goes in layer 4.

Four gates, four layers. Nothing runs at the same time. The measure-all row adds one more layer. So the Lab reports depth 5 and two-qubit depth 3.

But those last two CX gates don't really need to wait for each other. After layer 2, q0 and q1 are both part of the linked chain. So you can grow the chain from both of them at once. CX 0,2 and CX 1,3 touch different pairs of qubits, so ASAP layering puts them in the same layer. You get the same final state and the same gate count, but one layer less. On hardware, that means one layer less error and one layer less time for the qubits to fade.

What does this look like on real hardware?

Depth is time on the clock, and every device gives you two budgets.

The first is the coherence budget. Coherence is how long a qubit holds its state. A superconducting qubit holds its state for a time called T1, in the hundreds of microseconds. An entangling gate takes tens to hundreds of nanoseconds. (A nanosecond is a thousandth of a microsecond.) So in principle, thousands of layers fit. See the T1/T2 metric page.

The second is the fidelity budget, and it runs out much sooner. At 99.5% success per two-qubit gate, about 140 of them cut in half the chance that your circuit ran without a single two-qubit mistake. (0.995 multiplied by itself 140 times is about 0.5.)

Trapped-ion machines flip the trade. Their qubits hold their state for seconds or more. But their entangling gates are roughly a thousand times slower. You get fewer layers per second but more accuracy per layer. Neither kind simply wins. That is why the two-qubit count of your circuit matters more than any single spec number.

Every device profile in the QPU database lists two-qubit fidelity and coherence, with the source and date. The Lab's compare tab compiles your circuit for different wiring layouts. It reports exactly the numbers from this lesson. The next lesson covers the main reason those numbers grow in the first place: connectivity.

Primary sources & further reading