Circuit depth and width

Width is the easy one: the number of qubits the circuit touches. Depth is the interesting one. A circuit is a dependency graph — an operation must wait for every earlier operation that touches any of its qubits, and operations on disjoint qubits can run at the same time. Depth is the length of the critical path through that graph: the number of time steps left after everything parallelizable has been parallelized.

If you have ever scheduled build jobs, you already have the right intuition. Gate count is total work; depth is wall-clock time.

QPU137 computes depth by ASAP layering — as soon as possible: walk the operations in order and place each one in the earliest layer where all of its qubits are free. Every operation occupies one layer on every qubit it touches; a barrier forces a layer boundary but adds no depth; a measurement counts as one layer. The Lab shows depth, two-qubit ops, and two-qubit depth live as you edit, and the full definition lives on the circuit-depth metric page.

On today's devices, typical error rates sit in different decades: single-qubit gates around 0.01–0.1%, two-qubit entangling gates around 0.1–2%, and readout around 0.5–3% per measured qubit. The exact figures vary by platform and drift with calibration, but the ordering does not: the entangling gates are the expensive ones, roughly ten times worse than single-qubit gates on every current architecture.

Errors compound multiplicatively. Run 50 entangling gates at 99% fidelity each and the probability that none of them failed is 0.99^50 ≈ 0.60 — a coin flip's worth of signal gone before readout errors are even counted. That is why serious tools report the two-qubit count separately from the total, and why two-qubit depth — the number of layers containing at least one entangler — is the single best predictor of whether a circuit's output is signal or noise.

To be precise about what kind of claim this is: in the mathematical model, gates are exact and depth is free — those are theorems. The error rates above are measured properties of current machines. They improve year on year, and none of them is a law of nature.

Walk the circuit above. H on q0 goes in layer 1. CX 0,1 needs q0, so layer 2. CX 1,2 needs q1, so layer 3. CX 2,3 needs q2, so layer 4. Four gates, four layers — a fully serial circuit. The measure-all row adds one more layer, so the Lab reports depth 5 and two-qubit depth 3.

But the last two CXs do not actually depend on each other's targets. Once q0 and q1 are both part of the entangled chain (after layer 2), the state can be extended from both of them at once: CX 0,2 and CX 1,3 touch disjoint pairs, so ASAP layering puts them in the same layer. Same final state, same gate count — one layer shallower. On hardware, that is one layer less error and one layer less decoherence.

Depth is wall-clock time, and every device hands you two budgets. The coherence budget: a superconducting qubit holds its state for T1 in the hundreds of microseconds while an entangling gate takes tens to hundreds of nanoseconds, so thousands of layers fit in principle — see the T1/T2 metric page. The fidelity budget bites far sooner: at 99.5% per entangler, about 140 entangling gates halve the probability that your circuit ran without a single two-qubit fault.

Trapped-ion machines invert the trade: coherence of seconds or more, but entangling gates roughly a thousand times slower. Fewer layers per second, more fidelity per layer. Neither column wins outright — which is exactly why the two-qubit count of your circuit matters more than any single spec number.

Every device profile in the QPU database lists two-qubit fidelity and coherence with source and date, and the Lab's compare tab compiles your circuit against different coupling architectures and reports exactly the metrics from this lesson. The next lesson covers the main reason those numbers grow in the first place: connectivity.