Circuit depth

A quantum circuit is a quantum program drawn as a diagram. Each qubit is a line. Each gate (operation) is a box on one or more lines. Some gates can run at the same time, because they touch different qubits. Others must wait, because they use a qubit that an earlier gate is still using.

Depth counts the steps when you pack gates as early as they can go. Each step is called a layer. Two gates can share a layer only if they touch different qubits. So depth is the length of the longest chain of gates that must happen one after another. Depth is different from gate count, the total number of gates. It is also different from width, the number of qubits.

Depth is a property of a circuit, not of a machine. No spec sheet lists "the depth" of a processor. But a machine's figures decide how deep a circuit it can run before errors win.

An everyday example. Think of cooking dinner with helpers. You can boil water, chop onions and set the table at the same time. But you cannot fry the onions until they are chopped. Depth is the number of rounds dinner takes when everyone works in parallel. It is set by the longest chain of steps that must wait for each other.

Where the example breaks. In a kitchen, a long step takes longer. In a depth count, every layer counts as 1, whether it holds a quick single-qubit gate or a slow two-qubit gate. Also, some real machines cannot run every gate side by side, even when the qubits differ. On those machines, run time depends more on gate count than on depth.

Two-qubit depth counts only the layers that contain at least one two-qubit gate. We always show it next to total depth. The reason is simple: on today's hardware, two-qubit gates cause most errors (see two-qubit gate fidelity). So two-qubit depth predicts result quality better than total depth.

QPU137 counts depth by ASAP layering ("as soon as possible"). Every gate goes into the earliest layer where all its qubits are free. A gate takes one layer on every qubit it touches. A barrier, a marker that stops gates moving past it, forces a new layer but adds no depth of its own. We apply this same rule to every circuit.

Depth is not measured on hardware. It is computed from the circuit, by software. Compilers such as Qiskit and TKET each have a depth function. But tools make different choices about what counts:

• Do measurements count as a layer? Do barriers?
• Is the count for all gates, or only two-qubit gates?
• Is it counted before or after the circuit is compiled for a real machine?

The last question matters most. Compiling (also called transpiling) turns your gates into the machine's native gates. It also fixes up gates between qubits that are not wired together. It does this by adding SWAP gates that move qubit states next to each other. One SWAP is usually built from three CNOT gates. So compiling can make a circuit much deeper. The same circuit can honestly be "depth 8" before compiling and "depth 31" after. Our compilation comparison shows this for your own circuit on different machines.

For background on why depth limits today's machines, see Preskill, 2018.

Two depth numbers are not directly comparable when:

1. One is logical and one is compiled. "Logical" means the circuit as you wrote it. "Compiled" means after it was turned into native gates and routed. Compiled depth is almost always larger.
2. They were compiled for different machines. Each machine has its own native gates and wiring. A chip where every qubit can reach every other needs fewer SWAPs than one where each qubit has two or three neighbours.
3. They count different things. Total depth, two-qubit depth, and depth with or without measurements are different numbers.
4. Different compilers or settings were used. Compilers use different tricks and effort levels.

Also, the same depth does not mean the same run time. A layer of two-qubit gates takes nanoseconds on some machines and hundreds of microseconds on others. When a vendor or paper quotes a depth without saying how it was counted, our records say the convention is unknown. Our own compiler is a documented reference implementation, not a vendor compiler, so its depths show the effect of the hardware, not the best possible result.

Take 4 qubits, named q0 to q3. The circuit has 7 gates:

• An H gate on each of the 4 qubits. (H is a single-qubit gate.)
• A CNOT on q0 and q1, and a CNOT on q2 and q3.
• A CNOT on q1 and q2.

Now pack them into layers:

• Layer 1: all four H gates. They touch different qubits, so they fit together.
• Layer 2: CNOT(q0, q1) and CNOT(q2, q3). Again, no shared qubits.
• Layer 3: CNOT(q1, q2). It uses q1 and q2, which were busy in layer 2, so it must wait.

So gate count = 7, total depth = 3, and two-qubit depth = 2.

What compiling can do. Say the machine's wiring does not connect q1 and q2. The compiler adds one SWAP to bring the states together. If that SWAP is 3 CNOTs, it can add 3 more two-qubit layers. Two-qubit depth goes from 2 to 5.

From depth to time. Say a compiled circuit has 20 two-qubit layers and runs on ibm_brisbane. Its record lists a median ECR gate time of 660 ns (IBM calibration data, reported in a third-party paper). Then 20 × 660 ns = 13,200 ns = 13.2 µs. That record's median T2 is 129.77 µs, so the circuit uses about 13.2 ÷ 129.77 ≈ 10% of it. This is a rough size. It ignores single-qubit gates and readout time.

You can build this exact circuit in the Lab and see its depth counted.

Our QPU pages do not list depth, because depth belongs to circuits. They list the figures that decide how much depth a machine can handle: gate duration, coherence, and two-qubit gate quality. These records all include a two-qubit gate duration:

• ibm_brisbane: median ECR gate time of 660 ns, from IBM calibration data reported in a third-party review.
• Rigetti Ankaa-3: vendor-reported median iSWAP gate time of 72 ns.
• IonQ Forte: vendor-reported two-qubit gate time of ~900 µs, from a peer-reviewed paper, averaged over a 30-qubit chain.

Multiply two-qubit depth by the gate time, and compare it with T1 and T2. Multiply the error per gate by the number of gates, using two-qubit fidelity. Those two checks tell you most of what depth means on a given machine.

To learn depth step by step, try the lesson on circuit depth and width or the course chapter on circuit depth. For how the hardware side works, see the Inside Quantum Processors course.