Two-qubit gates
A two-qubit gate makes the operation on one qubit conditional on another. CX applies an X to the target exactly when the control is 1 — and because control and target are different roles, CX on [0,1] and CX on [1,0] are different gates. CZ is the exception: it only flips the sign of the both-qubits-1 amplitude, which makes it symmetric.
What does 'controlled' actually mean?
CX — controlled-X, also called CNOT — acts on two qubits with different roles. The control is left untouched; the target gets an X applied exactly when the control is 1:
- control 0 → target unchanged
- control 1 → target flipped
One thing 'controlled' does not mean: the gate does not measure the control. If the control is in superposition, CX acts on each component of the state separately — the branch where the control is 0 leaves the target alone, the branch where it is 1 flips it — and both branches stay in play. That per-branch action is what the runs below make visible.
Two notation facts you need for every circuit on this site: the control is always listed first (CX on [0, 1] means q0 controls, q1 is the target), and in result histograms the right-hand bit is q0. Because the roles differ, CX on [0, 1] and CX on [1, 0] are different gates — the second and third runs prove it, starting from the same state each time: an H on q0, nothing on q1.
Why is CZ symmetric when CX isn't?
CZ applies a Z to the target when the control is 1 — equivalently, it flips the sign of the |11⟩ component's amplitude and touches nothing else. Notice that this description never says which qubit is which: 'both qubits are 1' is a symmetric condition. CZ on [0, 1] and CZ on [1, 0] are the same matrix, so CZ has no meaningful control/target distinction at all.
CZ and CX are close relatives: wrap the target of a CZ in two H gates and you get exactly a CX. The next circuit builds a CX that way — q0 set to 1, then H, CZ, H on q1 — and behaves identically to the X-then-CX run above.
What do two-qubit gates cost on real hardware?
Two-qubit gates are where the error budget goes. On current devices a single-qubit gate typically errs around 0.01–0.1% per use; a two-qubit gate is roughly ten times worse or more, and slower too. Circuit quality on real hardware is largely a question of how many two-qubit gates you can avoid.
Hardware also has a native preference. Most QPUs don't implement CX directly: IBM's superconducting devices use ECR, Google's and IQM's use CZ, and trapped-ion machines use Mølmer–Sørensen-style gates — the compiler builds your CX from the native gate plus single-qubit gates, exactly like the H·CZ·H construction you just ran. Connectivity matters too: if two qubits aren't physically coupled, the compiler inserts SWAP gates (three CXs each) to bring the data together. Compare native gate sets and connectivity on the hardware comparison.