Connectivity costs
On most processors each qubit can interact with only a few neighbors, so a two-qubit gate between distant qubits must be routed: the compiler inserts SWAP gates to move the states next to each other, and every SWAP costs three CX. That is how a circuit with 5 entangling gates on paper becomes 14 on a lattice — and stays 5 on an all-to-all machine.
Why can't every qubit talk to every qubit?
Superconducting qubits are circuit elements printed on a chip. A two-qubit gate needs a physical coupler between the two qubits, and couplers only reach neighbors. More couplers per qubit would improve connectivity but hurt everything else — crosstalk, frequency collisions, control complexity. IBM's heavy-hex lattice caps every qubit at three neighbors on purpose: it trades connectivity for cleaner gates.
Trapped ions work differently. Ions in a chain interact through shared motional modes, so any pair can be entangled directly — all-to-all connectivity within the chain. Neutral-atom machines can physically move atoms between gate layers, rewiring the connection graph mid-circuit; that is a demonstrated capability on real hardware, paid for with slow movement steps.
So "how many qubits" is only half a spec. The other half is the coupling map: which pairs can actually interact. The QPU database records it per device.
What does the ideal simulator say?
Why does q4 read 0 — and what will hardware have to do?
First, the histogram. After the four chain CXs the state is a five-qubit GHZ state: an equal superposition of |00000⟩ and |11111⟩. The closing CX 0,4 flips q4 exactly in the branch where q0 is 1 — turning |11111⟩ into |01111⟩ and leaving |00000⟩ alone. So q4 ends up 0 in both branches and always reads 0 (the leftmost bit in the display). No mystery; just basis-state bookkeeping.
Now the hardware problem. A ring of five interactions cannot be laid out on a line or a tree so that every interacting pair is adjacent — on a sparse lattice, some CX in this circuit will target two qubits that are simply not coupled.
The compiler's fix is routing: insert SWAP gates to move quantum states across the chip until both operands of a gate sit on coupled qubits. A SWAP is not a cheap pointer exchange — it is built from three CX gates. Every SWAP the router inserts adds three entanglers to the error budget from the previous lesson.
What does the same circuit cost on three architectures?
Watch two numbers per row: SWAPs inserted, and the two-qubit count — 5 logical entanglers stay 5 on all-to-all, but become 14 on both lattices (3 SWAPs × 3 CX = 9 extra).
Where did the extra gates go?
The arithmetic is exact: 5 logical entanglers + 3 SWAPs × 3 CX each = 14 two-qubit operations on both lattice targets. Depth grows too — on the heavy-hex target this six-operation circuit compiles to depth 16, because routed gates serialize: each SWAP must finish before the gate it enables can start.
The square-lattice row shows something else worth noticing: around a hundred total operations. Most of those are single-qubit rotations from basis translation, not routing — that is the subject of the next lesson. When you compare architectures for routing cost, read the two-qubit column; it is the one that predicts fidelity.
One honesty note: these numbers come from the QPU137 reference compiler, which is deliberately simple, documented, and deterministic. Vendor compilers use smarter placement and routing and often do better. The shape of the result — all-to-all pays no routing tax, lattices do — is robust; the exact counts are not universal constants.
What does this look like on real hardware?
Heavy-hex — at most three neighbors per qubit — is what IBM's deployed superconducting devices have used; square lattices with four neighbors appear across several superconducting vendors and in IBM's newer roadmap chips. Trapped-ion systems from IonQ and Quantinuum offer all-to-all connectivity within chains of dozens of qubits: zero SWAPs, but each entangling gate runs roughly a thousand times slower than a superconducting one. Neutral-atom machines rearrange atoms between gate layers — demonstrated on real hardware, not yet a universal production feature.
None of these simply wins. A sparse lattice with fast, high-fidelity gates can beat an all-to-all machine on circuits that fit its geometry, and lose on circuits that do not. Check a device's coupling map in the QPU database, see how the specs sit side by side — with their caveats — on the comparison page, and compile your circuit in the Lab's compare tab, exactly as the panel above did.