Connectivity costs
On most quantum chips, each qubit can only work directly with a few neighbors. So a two-qubit gate between far-apart qubits must be routed: the compiler adds SWAP gates to move the states next to each other, and every SWAP costs three CX gates. That is how a circuit with 5 two-qubit gates on paper becomes 14 on a grid-like chip, but stays 5 on a machine where every qubit can reach every other.
Why can't every qubit talk to every qubit?
Superconducting qubits are tiny circuits printed on a chip. A two-qubit gate needs a physical link, called a coupler, between the two qubits. Couplers only reach nearby qubits. Adding more couplers per qubit would improve connectivity (how many qubits each one can reach). But it would hurt everything else. Signals would leak between wires, which is called crosstalk. Qubit frequencies would clash. Control would get harder. IBM's heavy-hex layout limits every qubit to three neighbors on purpose. It gives up some connectivity to get cleaner gates.
Trapped ions work differently. Ions in a row all jiggle together, so they share a motion. That shared motion lets any pair be entangled directly. This is called all-to-all connectivity within the row. Neutral-atom machines can physically move atoms between layers of gates. That rewires the connections in the middle of a circuit. This has been shown on real hardware, but the moving steps are slow.
Think of a big office. In some offices you can only talk to the people at the desks next to you. To reach someone far away, you pass notes desk to desk. In other offices everyone can talk to everyone. Unlike notes, though, a qubit's state can't be copied. It has to be moved, one swap at a time.
So "how many qubits" is only half a spec. The other half is the coupling map, which shows which pairs can actually interact. The QPU database records it for each device.
What does the ideal simulator say?
Why does q4 read 0, and what will hardware have to do?
First, the chart. After the four chain CX gates, the state is a five-qubit GHZ state. That is an equal mix of |00000⟩ and |11111⟩. The closing CX 0,4 flips q4 only in the part where q0 is 1. It turns |11111⟩ into |01111⟩ and leaves |00000⟩ alone. So q4 ends up 0 in both parts. It always reads 0. (q4 is the leftmost bit in the display.) There's no mystery, just careful bookkeeping.
Now the hardware problem. These five links form a ring. You can't lay a ring out on a line or a tree so that every linked pair sits side by side. So on a chip with few couplers, some CX in this circuit will try to act on two qubits that simply aren't connected.
The compiler's fix is called routing. It adds SWAP gates to move quantum states across the chip. It keeps going until both qubits of a gate sit on connected spots. A SWAP is not a cheap label change. It is built from three CX gates. So every SWAP the router adds puts three more two-qubit gates into the error budget from the previous lesson.
What does the same circuit cost on three architectures?
Watch two numbers in each row: SWAPs added, and the two-qubit count. The 5 two-qubit gates stay 5 on all-to-all, but become 14 on both grid layouts (3 SWAPs × 3 CX = 9 extra).
Where did the extra gates go?
Let's do the arithmetic. It is exact. You start with 5 two-qubit gates. Then add 3 SWAPs × 3 CX each = 9. So 5 + 9 = 14 two-qubit gates on both grid layouts.
Depth grows too. On the heavy-hex layout, this six-gate circuit compiles to depth 16. That is because routed gates have to wait in line. Each SWAP must finish before the gate it makes possible can start.
The square-grid row shows something else. It has around a hundred gates in total. Most of those are single-qubit turns added by basis translation, which means rewriting gates into the ones the chip knows. They don't come from routing. That is the topic of the next lesson. When you compare layouts for routing cost, read the two-qubit column. It is the one that predicts accuracy.
One honesty note. These numbers come from the QPU137 reference compiler. It is kept simple, documented, and repeatable on purpose. Vendor compilers place and route more cleverly and often do better. The overall shape is solid: all-to-all pays no routing cost, and grid layouts do. The exact counts are not fixed rules.
What does this look like on real hardware?
Heavy-hex, with at most three neighbors per qubit, is what IBM's deployed superconducting devices have used. Square grids with four neighbors show up in chips from several superconducting makers, and in IBM's newer roadmap chips. Trapped-ion systems from IonQ and Quantinuum offer all-to-all connectivity within rows of dozens of qubits. That means zero SWAPs. But each entangling gate runs roughly a thousand times slower than a superconducting one. Neutral-atom machines move atoms around between gate layers. That has been shown on real hardware, but it is not yet a standard feature everywhere.
None of these simply wins. A sparse grid with fast, accurate gates can beat an all-to-all machine on circuits that fit its shape. It can lose on circuits that don't. Check a device's coupling map in the QPU database. See how the specs line up, with their warnings, on the comparison page. Then compile your circuit in the Lab's compare tab, just like the panel above did.