Reading hardware specs

Strip the marketing and a QPU spec page reduces to five figures:

• Two-qubit gate fidelity — the number to anchor on. Your compiled circuit multiplies by it once per entangler.
• T1 and T2 — how long a qubit holds energy and phase; your circuit's wall-clock time must be a small fraction of both.
• Readout fidelity — paid once per measured qubit, every shot.
• Qubit count — the headline number, and by itself it ranks nothing.
• The coupling map — how much routing your circuit will need (previous lessons).

Each figure is a claim measured under conditions the vendor chose. To use one you need three qualifiers: the method (how it was measured), the aggregation (best qubit, median, or mean), and the date (calibration drifts daily).

Suppose a device's best qubit pair reaches 99.9% two-qubit fidelity and the device median is 99.0%. Both numbers may appear in print — sometimes only the first. For a circuit with 20 entanglers, the difference is not cosmetic: 0.999^20 ≈ 0.98 on the hero pair, 0.99^20 ≈ 0.82 across typical pairs.

And your compiled circuit does not run on the hero pair. Routing spreads it across whatever region of the chip the mapper chose, so the median — or something worse, once crosstalk between simultaneous gates is counted — is what predicts your result. When a spec sheet does not say which aggregation a number is, that omission is itself information.

Multiply. At 99.5% per entangler, the chance all eight CXs above run cleanly is 0.995^8 ≈ 0.96; at 99.0% it is 0.99^8 ≈ 0.92. On hardware, the missing shots surface as outcomes the ideal circuit never produces — 10 and 11 — and as bias in the 00/01 balance. Then add readout: at 98% per qubit, about 4% of two-qubit shots contain a misread bit before any gate error is counted.

Time matters too, but differently here: eight serial CXs at roughly 300 ns each is about 2.4 µs, far below a T1 of hundreds of microseconds. For shallow circuits like this one, fidelity is the binding constraint, not coherence. At depths in the hundreds, the balance shifts — which is why you read T1/T2 next to the gate duration, never alone.

Standard randomized benchmarking measures a gate pair in isolation — no neighbors firing, no crosstalk. Real circuits run many entanglers at once, so isolated-pair numbers flatter the device. Layered metrics fix this: IBM's EPLG (error per layered gate) runs long chains of simultaneous two-qubit gates and reports the error per gate in that context — usually a worse number, and a more predictive one.

Other holistic figures answer different questions again: Quantum Volume compresses width, depth, and fidelity into one benchmark-defined number; IonQ's algorithmic qubits (#AQ) is derived from a basket of benchmark circuits. None of these are wrong — but they are answers to different questions, and numbers from different metric families must never be ranked against each other. A device with a higher #AQ is not thereby "better" than one with a higher EPLG-derived layer count.

This is where the series lands, so here is the full checklist, in the order that saves the most time. One: find the entangler fidelity and demand its three qualifiers — method, aggregation, date. A number missing any of them is a vendor claim you cannot verify, and should be weighted accordingly. Two: check who measured it. Vendor-published calibration data is a claim; an independent reproduction is verification; the two deserve different confidence. Three: check the coupling map and the native set, because they determine what your circuit compiles into — the count that the fidelity number multiplies against. Four: only then look at the qubit count.

Every record in the QPU database is built around this: each figure carries its source, method, and aggregation where the vendor disclosed them, says not publicly disclosed where they did not, and is stamped with a retrieval date. The comparison page puts devices side by side with a mandatory statement of why the numbers may not be directly comparable — because often they are not.

And the final move is the one no spec sheet can make for you: take your actual circuit into the Lab, read its compiled two-qubit count per architecture, and multiply by the fidelity you can verify. The best machine is not the one with the biggest headline — it is the one that minimizes your circuit's entangler bill.