Reading hardware specs

Take away the marketing and a QPU spec page comes down to five numbers:

• Two-qubit gate fidelity. Fidelity means how often a step does the right thing. This is the number to focus on. Your compiled circuit multiplies by it once per two-qubit gate.
• T1 and T2. These say how long a qubit holds its energy (T1) and its phase (T2). Your circuit's run time must be a small part of both.
• Readout fidelity. You pay this once per measured qubit, every shot.
• Qubit count. This is the headline number. On its own, it ranks nothing.
• The coupling map. This shows which qubits are wired together, and so how much routing your circuit will need (previous lessons).

Each number was measured in conditions the vendor chose. To use one, you need three facts about it:

1. The method: how it was measured.
2. The aggregation: how many results were rolled into one number. Is it the best qubit, the median (the middle value), or the mean (the average)?
3. The date: machines drift from day to day.

Say a device's best qubit pair reaches 99.9% two-qubit fidelity. Its median pair is at 99.0%. Both numbers may be printed. Sometimes only the first one is.

For a circuit with 20 two-qubit gates, the gap is big. Let's compute it:

• Best pair: 0.999^20 ≈ 0.98. About 98% of runs go cleanly.
• Typical pair: 0.99^20 ≈ 0.82. Only about 82% do.

Think of a sports team that reports only its fastest runner's time. That tells you little about how the whole team will do in a relay.

And your compiled circuit doesn't run on that star pair. Routing spreads it over whatever part of the chip the compiler picked. So the median is what predicts your result. It may even be worse than the median once you count crosstalk, which is gates that run at the same time disturbing each other. When a spec sheet doesn't say how a number was averaged, that silence tells you something too.

You multiply. Let's do the arithmetic for the eight CX gates above.

• At 99.5% per gate: 0.995^8 ≈ 0.96. So all eight run cleanly about 96% of the time.
• At 99.0% per gate: 0.99^8 ≈ 0.92. That is about 92%.

On hardware, the lost shots show up as answers the ideal circuit never gives, 10 and 11. They also show up as a lean in the 00/01 balance.

Then add readout. Say each qubit is read correctly 98% of the time. With two qubits, the chance both are read right is 0.98 × 0.98 ≈ 0.96. So about 4% of shots have a misread bit, before any gate error is counted.

Time matters too, but less here. Eight CX gates in a row at about 300 ns each take 8 × 300 = 2,400 ns. That is about 2.4 µs. A T1 of hundreds of microseconds is far longer. So for short circuits like this one, fidelity is the real limit, not coherence. When circuits get hundreds of layers deep, that balance changes. That is why you always read T1/T2 next to the gate time, never alone.

The standard test is called randomized benchmarking. It measures one gate pair by itself, with no neighbors running and no crosstalk. Real circuits run many two-qubit gates at once. So numbers from pairs tested alone make the device look better than it is. It is like timing a driver on an empty road and using that to guess rush-hour travel.

Layered metrics fix this. IBM's EPLG (error per layered gate) runs long chains of two-qubit gates at the same time. It reports the error per gate in that busy setting. The number is usually worse, and it predicts real results better.

Other all-in-one numbers answer other questions. Quantum Volume squeezes width, depth, and fidelity into one number defined by a test. IonQ's algorithmic qubits (#AQ) comes from a set of test circuits. None of these are wrong. But they answer different questions. Numbers from different kinds of metrics must never be ranked against each other. A device with a higher #AQ is not "better" just because of that than one with a higher EPLG-based layer count.

This is where the series ends, so here is the full checklist. It is in the order that saves you the most time.

One: find the two-qubit gate fidelity and ask for its three facts: method, aggregation, date. A number missing any of them is a vendor claim you can't check. Give it less weight.

Two: check who measured it. Calibration data the vendor publishes is a claim. A check by someone else is independent proof. The two deserve different levels of trust.

Three: check the coupling map and the native gate set. They decide what your circuit compiles into. That compiled count is what the fidelity number multiplies against.

Four: only then look at the qubit count.

Every record in the QPU database is built around this. Each number carries its source, method, and aggregation when the vendor shared them. It says not publicly disclosed when they did not. Each is stamped with the date we collected it. The comparison page puts devices side by side. It always states why the numbers may not be directly comparable, because often they are not.

The last step is one no spec sheet can do for you. Take your real circuit into the Lab. Read its compiled two-qubit count for each layout. Then multiply by the fidelity you can check. The best machine is not the one with the biggest headline. It is the one that keeps your circuit's two-qubit gate bill smallest.