Native gates and transpilation

A gate is not an instruction the hardware looks up — it is a physical control pulse (microwave, laser, or flux) that must be calibrated per qubit against daily drift. Calibrating a handful of pulses extremely well beats calibrating dozens badly, so every platform exposes a minimal native set and lets software build everything else from it.

Three representative bases, matching the three targets in the panel further down:

• RZ, SX, X + ECR — IBM-style heavy-hex devices. Any single-qubit gate becomes at most RZ·SX·RZ·SX·RZ.
• RZ, RX + CZ — square-lattice devices with tunable couplers.
• Ion-style rotations + MS — trapped ions: single-qubit rotations plus the Mølmer–Sørensen entangler.

One detail that matters for reading compiled counts: on most superconducting stacks RZ is virtual — implemented as a frame update in the control software, taking zero time and adding essentially zero error. A compiled circuit stuffed with RZ gates is much cheaper than its raw operation count suggests.

The three-gate sequence above equals H times a global phase factor. A global phase multiplies every amplitude by the same unit complex number, and measurement probabilities are squared magnitudes — so no experiment can tell the two apart. "Equal up to global phase" is exact equivalence for every observable purpose, and it is the standard a transpiler must meet: not approximately right, exactly right.

The translation rules are mechanical. A CX becomes a CZ conjugated by Hadamards on the target (which then decompose into the single-qubit basis). A CP — native on almost no machine — becomes two entanglers plus three RZ rotations. A SWAP becomes three entanglers. Each rule is small; they compound.

Not directly — count what actually costs. The square-lattice row totals 135 operations, but the majority are RZ gates, which are virtual on most such hardware: near-free. The honest comparison is the two-qubit column: 9 entanglers on all-to-all versus 15 on either lattice, where the extra 6 are the two routing SWAPs.

The breakdown is exact here. Each of the three CP gates costs 2 entanglers (6 total) and the final SWAP costs 3 — that is the 9 on all-to-all. Add 2 routing SWAPs × 3 CX on the lattices and you get 15. Two-qubit count and two-qubit depth carry the error budget; single-qubit totals mostly do not.

As before, these are reference-compiler numbers — documented and reproducible; vendor transpilers optimize harder and often do better. What no compiler can do is translate for free: every target pays the entangler cost of CP and SWAP in its own coin.

Every device profile in the QPU database records the native set where the vendor discloses it. The first thing to look for is the entangler — ECR or CZ on superconducting chips, MS on ions — because its fidelity is the number your whole compiled circuit multiplies by, once per two-qubit op.

Two consequences for reading published numbers. First, gate counts are meaningless across devices unless counted in the same basis: the same circuit is honestly "7 gates" logical and "58 operations" compiled, and the circuit-depth metric page spells out the convention trap. Second, a vendor quoting performance "per gate" may mean a native gate that is only a third of the SWAP your circuit actually needs.

The Lab's code export writes your circuit for each target family, and its compare tab shows the translated counts live — the same panel you used above. The last lesson in this series, reading hardware specs, puts the fidelity numbers behind these counts under the microscope.