Native gates and transpilation
No quantum chip runs H, CP, or SWAP directly. Each one offers a small, carefully tuned native set of gates, for example RZ, SX and X plus one two-qubit gate. The compiler rewrites your circuit into that set exactly, except for a global phase that no one can ever measure. That rewriting is why a seven-gate circuit can honestly become 31 native steps on one kind of chip and 135 on another.
Why doesn't hardware speak H?
A gate is not a command the hardware looks up in a list. It is a physical control pulse, such as a burst of microwaves, a laser flash, or a magnetic nudge. Each pulse has to be tuned for each qubit, because the hardware drifts from day to day. This tuning is called calibration. Tuning a few pulses very well beats tuning dozens badly. So every platform offers a small native set of gates it really performs. Software builds every other gate out of those.
Think of a piano. It can only play its keys. Yet any song can be written as a list of keys. The piano doesn't need a special button for each song. Unlike a song, though, a rewritten circuit must be exactly the same as the original, not just close.
Here are three common native sets. They match the three targets in the panel further down:
- RZ, SX, X + ECR: IBM-style heavy-hex devices. Any single-qubit gate becomes at most RZ·SX·RZ·SX·RZ.
- RZ, RX + CZ: square-grid devices with adjustable couplers.
- Ion-style rotations + MS: trapped ions. They use single-qubit turns plus the Mølmer–Sørensen two-qubit gate.
One detail matters when you read compiled counts. On most superconducting systems, RZ is virtual. The control software just updates its reference for later pulses. It takes no time and adds almost no error. So a compiled circuit full of RZ gates is much cheaper than its raw count suggests.
Is RZ·SX·RZ really a Hadamard?
If the gates are different, how is the circuit the same?
The three-gate sequence above equals H times a global phase. A global phase multiplies every amplitude by the same number of size 1. (An amplitude is the number that sets how likely an answer is.) The chance of each answer comes from squaring the size of its amplitude. So a shared factor of size 1 changes nothing: 1 × 1 = 1. No experiment can tell the two circuits apart.
"Equal except for global phase" means exactly equal for anything you could ever observe. That is the bar a transpiler (the part of the compiler that rewrites gates) must clear. Not roughly right: exactly right.
The rewriting rules are mechanical, like steps in a recipe:
- A CX becomes a CZ with a Hadamard on each side of the target. Those Hadamards then become native single-qubit gates.
- A CP (controlled phase) is native on almost no machine. It becomes two two-qubit gates plus three RZ turns.
- A SWAP becomes three two-qubit gates.
Each rule is small. But they add up.
How much does a small QFT grow?
A 3-qubit quantum Fourier transform: seven gates as written, four of them two-qubit gates. Even on all-to-all, with zero SWAPs, rewriting alone gives 31 native steps with 9 two-qubit gates. The grid layouts add routing on top.
Do bigger native counts mean worse results?
Not directly. Count what really costs. The square-grid row adds up to 135 steps. But most of them are RZ gates, which are virtual on most such hardware. They are almost free. The honest comparison is the two-qubit column. It shows 9 two-qubit gates on all-to-all and 15 on either grid layout. The extra 6 come from two routing SWAPs.
Let's work the numbers. They are exact here.
- Each of the three CP gates costs 2 two-qubit gates: 3 × 2 = 6.
- The final SWAP costs 3.
- So all-to-all needs 6 + 3 = 9.
- The grids add 2 routing SWAPs × 3 CX = 6. That gives 9 + 6 = 15.
Two-qubit count and two-qubit depth carry the error budget. Single-qubit totals mostly don't.
As before, these are numbers from our reference compiler. They are documented and repeatable. Vendor transpilers work harder and often do better. But no compiler can rewrite for free. Every target pays the two-qubit cost of CP and SWAP in its own way.
What does this look like on real hardware?
Every device profile in the QPU database records the native set when the vendor shares it. The first thing to look for is the two-qubit gate. That is ECR or CZ on superconducting chips, and MS on ions. Its fidelity (how often it works right) is the number your whole compiled circuit multiplies by, once per two-qubit gate.
This changes how you read published numbers in two ways. First, gate counts from different devices mean nothing unless they are counted with the same native set. The same circuit is honestly "7 gates" as written and "58 operations" once compiled. The circuit-depth metric page explains this trap. Second, a vendor quoting results "per gate" may mean a native gate that is only a third of a SWAP your circuit actually needs.
The Lab's code export writes your circuit for each target family. Its compare tab shows the rewritten counts live, just like the panel you used above. The last lesson in this series, reading hardware specs, takes a close look at the fidelity numbers behind these counts.