IBM Eagle, Condor, Heron: IBM's Quantum Chips Compared

IBM names its quantum chips after birds. Each name is a family, a chip design. Each family can have several revisions, marked r1, r2, r3. Each real machine that runs one of those chips gets a city name, like ibm_brisbane or ibm_boston.

So there are three layers of names:

• Family: Eagle, Osprey, Condor, Heron, Nighthawk.
• Revision: for example, Heron r3 is the third version of Heron.
• Machine: for example, ibm_boston is one real Heron r3 machine.

This matters when you read a number. A figure for one machine is not a figure for the whole family. Two machines with the same chip can have different error rates on the same day.

We track four IBM records. Each one below links to its own page, with every source. All qubit counts here are vendor-reported, meaning IBM published them.

Eagle was IBM's 127-qubit chip. Our record is ibm_brisbane, an Eagle r3 machine. IBM lists it as retired on 2025-11-03. It no longer accepts jobs.

Eagle uses superconducting qubits. These are tiny circuits of metal, cooled until electricity flows with no resistance. Its qubits sit in a heavy-hex layout. Each qubit links to only two or three neighbors. A review paper says this design cuts errors from qubits bumping into each other. The cost is that far-apart qubits must pass data through the middle. Our lesson on connectivity costs shows what that does to a circuit.

Eagle's native gates, the only gates the chip really runs, were ECR, RZ, SX and X. ECR is its two-qubit gate.

Because Eagle is retired, IBM no longer shows live numbers for it. Our figures come from two outside papers that reported IBM's own calibration data from mid-2024:

• Median two-qubit (ECR) error: 8.335E-3, as of 2024-07-03. That is about 8 failures per 1,000 gates.
• Median T1: 217.83 microseconds. Median T2: 129.77 microseconds. These are coherence times, how long a qubit holds its state.
• Median readout error: 1.240E-2, about 12 wrong reads per 1,000.
• Median two-qubit gate time: 660 nanoseconds.

Calibration drifts every day. So treat these as a snapshot from 2024, not as a fixed spec.

Condor is the chip behind the search term "IBM Condor". IBM announced it on 2023-12-04 as a 1,121-qubit processor. That is still the largest qubit count of any IBM chip in our data. You can see the record at IBM Condor.

IBM said Condor pushed chip design with a 50% increase in qubit density. It also said Condor had more than a mile of cryogenic wiring inside one fridge. But IBM described its results in only one line. In IBM's words, Condor has "performance comparable to our previous 433-qubit Osprey". IBM called it "an innovation milestone, solving scale and informing future hardware design".

Here is what IBM did not publish for Condor, as far as our search found:

• Two-qubit gate fidelity: not publicly disclosed.
• T1 and T2 coherence times: not publicly disclosed.
• Readout fidelity: not publicly disclosed.

Condor was never offered on IBM's cloud. It is not in the live fleet list. It is not in the list of retired cloud machines either. So you could never run a circuit on it. Condor was a test of how big a chip IBM could build, not a product.

We will not guess the missing numbers. If a figure is not disclosed, our page says so.

Heron came out at the same time as Condor, in the same IBM post from December 2023. It went the other way. The first Heron had 133 qubits, far fewer than Condor. IBM's post described Heron as having "fixed-frequency qubits with tunable couplers". A tunable coupler is a small switch between two qubits. It can link them for a gate, then unlink them so they stop disturbing each other.

Heron is now in its third revision. IBM's docs say r3 adds "targeted manufacturing improvements that directly impact coherence, gate fidelity, and readout performance". The first Heron r3 machine, ibm_pittsburgh, launched on 31 July 2025.

Our Heron r3 record is ibm_boston. Here is what IBM's public fleet table showed on 2026-08-19. All of it is vendor-reported:

• 156 programmable qubits. The same page lists 332 physical qubits in total. IBM now counts the qubits you can program apart from all the qubits on the chip.
• Best two-qubit error: 6.43E-4. That is the single best link on the chip. It works out to about 6 failures per 10,000 gates.
• Layered two-qubit error: 2.54E-3. This is an average error per gate across a chain of 100 qubits, run in layers. About 25 failures per 10,000 gates.
• Median readout error: 3.418E-3.
• Speed: 340K CLOPS, circuit layers run per second, by IBM's own test.

T1, T2, one-qubit gate error and gate time are not shown on IBM's public pages for ibm_boston. We list them as not publicly disclosed.

Look again at ibm_boston. The best link has an error of 6.43E-4. The layered average is 2.54E-3. The second is about four times the first. Both are true. They measure different things.

Think of a school's test scores. "Top student: 99%" and "class average: 80%" are both true. They answer different questions. The best link is the top student. The layered number is closer to how the whole class does when everyone works at once.

This is also why you must not line up numbers from different methods. Eagle's 8.335E-3 is a median from 2024 papers. Heron r3's 6.43E-4 is a best single link from 2026. Putting them side by side would make the gap look bigger than it is. Our data has no Eagle figure measured the same way as Heron's. So we cannot give you a fair "how much better" number. Our guide to two-qubit fidelity explains these labels in more depth.

Nighthawk is IBM's newest family in our data. Our record is ibm_miami, a Nighthawk r1 machine. It has 120 qubits, fewer again than Heron r3.

The big change is the layout. Nighthawk puts its qubits on a square grid. Each qubit links to its four nearest neighbors, using 218 tunable couplers. IBM says that is over 20 percent more couplers than Heron. More links mean fewer extra moves when two far-apart qubits need to talk.

IBM also claims the chip can run circuits with up to 5,000 two-qubit gates. IBM did not state how it measured that. Its roadmap aims for 7,500 gates in 2026, 10,000 in 2027 and 15,000 in 2028. Those are roadmap claims, plans for the future, not results.

On 2026-08-19, IBM's fleet table showed a best two-qubit error of 8.61E-4 and a layered error of 9.69E-3 for ibm_miami. It also showed 24K CLOPS. It was an early-access machine then. Its layered error was clearly higher than the Heron r3 machines on the same day.

IBM has not put it in exactly those words. But the record is plain. The largest chip, Condor, came in 2023 with 1,121 qubits. The public chips that followed had 156 and 120.

The reason is errors. Every gate has a small chance to fail. A useful circuit has thousands of gates. So the chance of a clean run shrinks with every gate you add.

Here is a worked example with round numbers, not IBM's. Say every two-qubit gate fails 1 time in 100. Then the chance that one gate works is 0.99. The chance that 1,000 gates all work is 0.99 multiplied by itself 1,000 times. That is about 0.00004. Almost every run would contain an error. Now say each gate fails 1 time in 10,000. Then 1,000 gates all work about 90% of the time.

Adding qubits does not fix that. A chip with 1,000 noisy qubits still cannot run a long circuit. So IBM's roadmap now measures progress by how many gates its processors can run, not by qubit totals. Its newer chips aim to hold more gates, not more qubits.

There is a longer-term reason too. The way out of errors is error correction, which groups many physical qubits into one reliable logical qubit. That only works if each physical qubit is good enough first. IBM's plans for large error-corrected machines are roadmap claims. Our page on fault tolerance sorts what has been shown from what is only planned.

You cannot pick Eagle or Condor. Eagle is retired. Condor was never public. Today the choice is between Heron r3 machines and early-access Nighthawk machines on IBM's cloud.

A few simple tips:

• Check the date on every figure. IBM's numbers change with each calibration.
• Check the label: best, median or layered. Only compare like with like.
• Think about layout. Heron's heavy-hex links two or three neighbors. Nighthawk's grid links four. Your circuit's shape decides which costs fewer extra gates. Our connectivity chapter shows how to reason about it.

You can put ibm_boston next to machines from other makers on our compare page. It warns you when two numbers were measured in different ways.